The present invention is useful in many types of circuits employing bipolar input stages to facilitate understanding, however, the following explanation will refer specifically to the input stage of an operational amplifier, it being understood that the invention is applicable to other types of devices as well.
Operational amplifiers are typically considered to comprise at least three stages: an input stage, an intermediate stage and an output stage. The characteristics of an operational amplifier's input stages are among the most critical factors which affect the operational amplifier's voltage gain performance. Error effects introduced in the input stage receive maximum amplification; error effects introduced in later stages are amplified to a much lesser degree.
FIG. 1 shows what is typically called a 741 input stage for an operational amplifier. It is a cascoded NPN PNP input stage. Such input stages are characterized in that they comprise a pair of NPN input transistors Q1 and Q2 cascoded with a pair of PNP transistors Q3 and Q4. They further comprise a dual collector PNP transistor Q5 having a first collector 11 coupled to the bases 13 and 14 of the PNP transistors Q3 and Q4, respectively, and a second collector 12 coupled to the collectors 15 and 16 of the NPN transistors Q1 and Q2, respectively. The two collector regions of transistor Q5 are of equal size and characteristics (i.e , ratioed 1:1) such that the current flowing through one collector terminal is approximately equal to the current flowing through the other collector terminal. Further, the base 18 of the dual collector transistor Q5 is also coupled to the collectors 15 and 16 of transistors Q1 and Q2. The emitter 20 of transistor Q5 is directly coupled to the positive voltage source (V+) of the operational amplifier, applied on line 15. The bases 21 and 22 of NPN transistors Q1 and Q2 are coupled to the non-inverting input 17 and inverting input 19, respectively, of the operational amplifier.
Theoretically, the inputs 17 and 19 to an operational amplifier are a infinite impedance as seen by the external circuitry such that no current flows into either input. However, as is obvious from FIG. 1, a small but frequently non negligible bias current, I/.beta..sub.n, flows into the bases 21 and 22 of transistors Q1 and Q2 (.beta..sub.n representing the current gain, or "beta", of the transistors).
Referring now to FIG. 2, an operational amplifier 23 is shown embodied in a circuit which operates essentially as a voltage controlled voltage source--i.e., an amplifier with voltage gain. Using ideal (unrealizable) components, the voltage response of the operational amplifier in this circuit is given by the equation ##EQU1## The assumed ideal components include the operational amplifier 23, which has zero input current and infinite input impedance. However, as can be seen from FIG. 1, the inverting input 19 of the operational amplifier is coupled to the base 22 of transistor Q2 and therefore, in fact, a small bias current flows into the inverting input 19. In the gain equation above, this bias current has obviously been ignored; the equation, therefore, is merely an approximation of the operation of the physical circuit. Although small, this bias current causes the circuit performance to vary from the ideal performance characteristics given by the equation above; sometimes the departure from ideal is of an unacceptable magnitude. A simple resistive circuit injecting a current equal to the bias current could be added, but such a circuit would be unacceptable since it would lower the input impedance.
A few attempts have been made in the prior art to provide, in operational amplifiers, input stage circuitry to compensate for bias current, so as to minimize or reduce this error. One such scheme is exemplified in the OP27 operational amplifier of Precision Monolithics Inc. of Santa Clara, Calif., shown in FIG. 3. Block 28 denotes this bias current cancellation circuitry employed in this particular scheme. A description of the operation of this bias current cancellation circuitry is found in G. Erdi, Amplifier Techniques for Combining Low Noise, Precision, and High Speed Performance, IEEE Journal of Solid State Circuits, Vol. SC-16, No. 6, December 1981, p 653. Although this method is effective, as can be seen from FIG. 3, it requires eleven transistors and a substantial penalty in semiconductor area and price.
Other methods of reducing or eliminating input stage bias currents are available, yet have various drawbacks. One method of reducing bias currents is to use FET or JFET components in the input stage. FETs and JFETs have substantially smaller bias currents than do bipolar transistors. However, such components are significantly noisier and are more prone to drift than bipolar transistors. In many situations, the latter condition outweighs the reduction in bias current. Another method known in the prior art is the use of "super .beta." components to replace the normal bipolar components. However, these components display low breakdown voltage, which drastically limits their practical use in operational amplifiers. Further, super .beta. input transistors are undesirable because the noise performance of a super .beta. transistor is considerably worse than that of an equivalent NPN transistor.
Therefore, it is an object of the present invention to provide an inexpensive apparatus and technique for compensating for bias currents in NPN PNP input stages of operational amplifiers.
It is a further object of the present invention to provide an apparatus which injects bias current into the bases of the input transistors of an input stage while maintaining a high input impedance.